333 tm march 1997 82C88 cmos bus controller features ? compatible with bipolar 8288 ? performance compatible with: - 80c86/80c88 . . . . . . . . . . . . . . . . . . . . . . . . . . (5/8mhz) - 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8mhz) - 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8mhz) -8089 ? provides advanced commands for multi-master busses ? three-state command outputs ? bipolar drive capability ? scaled saji iv cmos process ? single 5v power supply ? low power operation - iccsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 a (max) - iccop . . . . . . . . . . . . . . . . . . . . . . . . . 1ma/mhz (max) ? operating temperature ranges - c82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c - i82C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c - m82C88 . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c description the intersil 82C88 is a high performance cmos bus con- troller manufactured using a self-aligned silicon gate cmos process (scaled saji iv). the 82C88 provides the control and command timing signals for 80c86, 80c88, 8086, 8088, 8089, 80186, and 80188 based systems. the high output drive capability of the 82C88 eliminates the need for addi- tional bus drivers. static cmos circuit design insures low operating power. the intersil advanced saji process results in performance equal to or greater than existing equivalent products at a signifi- cant power savings. pinouts 20 lead pdip, cerdip top view 20 lead plcc, clcc top view ordering information part number package temperature range pkg. no. cp82C88 20 ld pdip 0 o c to +70 o ce20.3 cp82C88-10 0 o c to +70 o ce20.3 ip82C88 -40 o c to +85 o ce20.3 cs82C88 20 ld plcc 0 o c to +70 o cn20.35 is82C88 -40 o c to +85 o cn20.35 cd82C88 20 ld cerdip 0 o c to +70 o cf20.3 id82C88 -40 o c to +85 o cf20.3 md82C88/b -55 o c to +125 o cf20.3 8406901ra smd# f20.3 mr82C88/b 20 pad clcc -55 o c to +125 o cj20.a 84069012a smd# j20.a 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 iob clk ale gnd dt/ r aen mrdc amwc mwtc s1 v cc mce/pden den cen iorc aiowc iowc inta s0 s2 4 5 6 7 8 9101112 13 3 2 1 20 19 15 14 18 17 16 ale dt/ r aen mrdc amwc gnd iorc aiowc iowc mwtc v cc iob clk s1 s0 den cen mce/pden inta s2 fn2979.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
334 functional diagram pin description pin symbol number type description v cc 20 v cc : the +5v power supply pin. a 0.1 f capacitor between pins 10 and 20 is recommended for decoupling. gnd 10 ground. s0 , s1 , s2 19, 3, 18 i status input pins: these pins are the input pins from the 80c86, 80c88,8086/88, 8089 processors. the 82C88 decodes these inputs to generate command and control signals at the appropriate time. when status pins are not in use (passive), command outputs are held high (see table1). clk 2 i clock: this is a cmos compatible input which receives a clock signal from the 82c84a or 82c85 clock generator and serves to establish when command/control signals are generated. ale 5 o address latch enable: this signal serves to strobe an address into the address latches. this sig- nal is active high and latching occurs on the falling (high to low) transition. ale is intended for use with transparent d type latches, such as the 82c82 and 82c83h. den 16 o data enable: this signal serves to enable data transceivers onto either the local or system data bus. this signal is active high. dt/r 4 o data transmit/receive: this signal establishes the direction of data flow through the transceivers. a high on this line indicates transmit (write to i/o or memory) and a low indicates receive (read from i/o or memory). aen 6 i address enable: aen enables command outputs of the 82C88 bus controller a minimum of 110ns (250ns maximum) after it becomes active (low). aen going inactive immediately three-states the com- mand output drivers. aen does not affect the i/o command lines if the 82C88 is in the i/o bus mode (iob tied high). cen 15 i command enable: when this signal is low all 82C88 command outputs and the den and pden con- trol outputs are forced to their inactive state. when this signal is high, these same outputs are enabled. iob 1 i input/output bus mode: when the iob pin is strapped high, the 82C88 functions in the i/o bus mode. when it is strapped low, the 82C88 functions in the system bus mode (see i/o bus and system bus sections). v cc gnd command signals multibus tm control input iob cen clk aen control signal generator den ale dt/r mce/pden command signal generator aiowc iowc amwc mwtc mrdc iorc s2 s1 s0 inta address latch, data transceiver, and interrupt control signals control logic status decoder 82C88 intel? is a registered trademark of intel corporation
335 functional description the command logic decodes the three 80c86, 8086, 80c88, 8088, 80186, 80188 or 8089 status lines (s0 , s1 , s2 ) to determine what command is to be issued (see table 1). i/o bus mode the 82C88 is in the i/o bus mode if the iob pin is strapped high. in the i/o bus mode, all i/o command lines iorc , iowc , aiowc , inta ) are always enabled (i.e., not depen- dent on aen ). when an i/o command is initiated by the pro- cessor, the 82C88 immediately activates the command lines using pden and dt/r to control the i/o bus transceiver. the i/o command lines should not be used to control the system bus in this configuration because no arbitration is present. this mode allows one 82C88 bus controller to han- dle two external busses. no waiting is involved when the cpu wants to gain access to the i/o bus. normal memory access requires a ?bus ready? signal (aen low) before it will proceed. it is advantageous to use the iob mode if i/o or peripherals dedicated to one processor exist in a multi-pro- cessor system. system bus mode the 82C88 is in the system bus mode if the iob pin is strapped low. in this mode, no command is issued until a specified time period after the aen line is activated (low). this mode assumes bus arbitration logic will inform the bus controller (on the aen line) when the bus is free for use. both memory and i/o commands wait for bus arbitration. this mode is used when only one bus exists. here, both i/o and memory are shared by more than one processor. command outputs the advanced write commands are made available to initiate write procedures early in the machine cycle. this signal can be used to prevent the processor from entering an unneces- sary wait state. aiowc 12 o advanced i/o write command: the aiowc issues an i/o write command earlier in the machine cycle to give i/o devices an early indication of a write instruction. its timing is the same as a read com- mand signal. aiowc is active low. iowc 11 o i/o write command: this command line instructs an i/o device to read the data on the data bus. the signal is active low. iorc 13 o i/o read command: this command line instructs an i/o device to drive its data onto the data bus. this signal is active low. amwc 8 o advanced memory write command: the amwc issues a memory write command earlier in the machine cycle to give memory devices an early indication of a write instruction. its timing is the same as a read command signal. amwc is active low. mwtc 9 o memory write command: this command line instructs the memory to record the data present on the data bus. this signal is active low. mrdc 7 o memory read command: this command line instructs the memory to drive its data onto the data bus. mrdc is active low. inta 14 o interrupt acknowledge: this command line tells an interrupting device that its interrupt has been acknowledged and that it should drive vectoring information onto the data bus. this signal is active low. mce/pden 17 o this is a dual function pin. mce (iob is tied low) master cascade enable occurs during an interrupt sequence and serves to read a cascade address from a master 82c59a priority interrupt controller onto the data bus. the mce signal is active high. pden (iob is tied high): peripheral data enable enables the data bus transceiver for the i/o bus that den performs for the system bus. pden is active low. pin description (continued) pin symbol number type description table 1. command decode definition s2 s1 s0 processor state 82C88 command 0 0 0 interrupt acknowledge inta 001read i/o port iorc 0 1 0 write i/o port iowc , aiowc 0 1 1 halt none 1 0 0 code access mrdc 1 0 1 read memory mrdc 1 1 0 write memory mwtc , amwc 111passive none 82C88
336 inta (interrupt acknowledge) acts as an i/o read during an interrupt cycle. its purpose is to inform an interrupting device that its interrupt is being acknowledged and that it should place vectoring information onto the data bus. the command outputs are: mrdc - memory read command mwtc - memory write command iorc - i/o read command iowc - i/o write command amwc - advanced memory write command aiowc - advanced i/o write command inta - interrupt acknowledge control outputs the control outputs of the 82C88 are data enable (den), data transmit/receive (dt/r ) and master cascade enable/ peripheral data enable (mce/pden ). the den signal determines when the external bus should be enabled onto the local bus and the dt/r determines the direction of data transfer. these two signals usually go to the chip select and direction pins of a transceiver. the mce/pden pin changes function with the two modes of the 82C88. when the 82C88 is in the iob mode (iob high), the pden signal serves as a dedicated data enable signal for the i/o or peripheral system bus. interrupt acknowledge and mce the mce signal is used during an interrupt acknowledge cycle if the 82C88 is in the system bus mode (iob low). during any interrupt sequence, there are two interrupt acknowledge cycles that occur back to back. during the first interrupt cycle no data or address transfers take place. logic should be provided to mask off mce during this cycle. just before the second cycle begins the mce signal gates a mas- ter priority interrupt controller?s (pic) cascade address onto the processor?s local bus where ale (address latch enable) strobes it into the address latches. on the leading edge of the second interrupt cycle, the addressed slave pic gates an interrupt vector onto the system data bus where it is read by the processor. if the system contains only one pic, the mce signal is not used. in this case, the second interrupt acknowledge signal gates the interrupt vector onto the processor bus. address latch enable and halt address latch enable (ale) occurs during each machine cycle and serves to strobe the current address into the 82c82/82c83h address latches. ale also serves to strobe the status (s0 , s1 , s2 ) into a latch for halt state decoding. command enable the command enable (cen) input acts as a command qual- ifier for the 82C88. if the cen pin is high, the 82C88 func- tions normally. if the cen pin is pulled low, all command lines are held in their inactive state (not three-state). this feature can be used to implement memory partitioning and to eliminate address conflicts between system bus devices and resident bus devices. 82C88
337 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range c82C88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to +70 o c i82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c m82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c thermal resistance (typical) ja ( o c/w) jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . 75 18 clcc package . . . . . . . . . . . . . . . . . . 85 22 pdip package . . . . . . . . . . . . . . . . . . . 75 n/a plcc package . . . . . . . . . . . . . . . . . . 75 n/a storage temperature range . . . . . . . . . . . . . . . . .-65 o c to +150 o c maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . +300 o c (plcc - lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. dc electrical specifications v cc = 5.0v 10%; t a = 0 o c to +70 o c (c82C88); t a = -40 o c to +85 o c (i82C88); t a = -55 o c to +125 o c (m82C88) symbol parameter min max units test conditions v ih logical one input voltage 2.0 2.2 - - v v c82C88, i82C88 m82C88 v il logical zero input voltage - 0.8 v vihc clk logical one input voltage v cc -0.8 - v vilc clk logical zero input voltage - 0.8 v v oh output high voltage command outputs 3.0 v cc -0.4 -v v i oh = -8.0ma i oh = -2.5ma output high voltage control outputs 3.0 v cc -0.4 -v v i oh = -4.0ma i oh = -2.5ma v ol output low voltage command outputs -0.5vi ol = +12.0ma output low voltage control outputs -0.4vi ol = +8.0ma i i input leakage current -1.0 1.0 av in = gnd or v cc , except s0 , s1 , s2 , dip pins 1-2, 6, 15 ibhh input leakage current-status bus -50 -300 av in = 2.0v, s0 , s1 , s2 (see note 1) io output leakage current -10.0 10.0 av o = gnd or v cc , iob = gnd, aen = v cc , dip pins 7-9, 11-14 iccsb standby power supply - 10 av cc = 5.5v, v in = v cc or gnd, outputs open iccop operating power supply current - 1 ma/mhz v cc = 5.5v, outputs open (see note 2) notes: 1. ibhh should be measured after raising the v in on s0 , s1 , s2 to v cc and then lowering to valid input high level of 2.0v. 2. iccop = 1ma/mhz of clk cycle time (tclcl) capacitance t a = +25 o c symbol parameter typical units test conditions cin input capacitance 10 pf freq = 1mhz, all measurements are referenced to device gnd cout output capacitance 17 pf 82C88
338 ac testing input, output waveform a.c. testing: all input signals (other than clk) must switch between v il -0.4v and v ih +0.4. clk must switch between 0.4v and v cc -0.4v. input rise and fall times are driven at 1ns/v. a.c. test circuit ac electrical specifications v cc = 5.0v 10%; t a = 0 o c to +70 o c (c82C88); t a = -40 o c to +85 o c (i82C88); t a = -55 o c to +125 o c (m82C88) symbol parameter 8mhz 10mhz 12mhz units test conditions min max min max min max timing requirements (1) tclcl clk cycle period 125 - 100 - 83 - ns (2) tclch clk low time 55 - 50 - 34 - ns (3) tchcl clk high time 40 - 37 - 34 - ns (4) tsvch status active setup time 35 - 35 - 35 - ns (5) tchsv status inactive hold time 10 - 10 - 5 - ns (6) tshcl status inactive setup time 35 - 35 - 35 - ns (7) tclsh status active hold time 10 - 10 - 5 - ns timing responses (8) tcvnv control active delay 5 45 5 45 5 45 ns 1 (9) tcvnx control inactive delay 10 45 10 45 10 35 ns 1 (10)tcllhale active delay (from clk)-20-20-20ns 1 (11) tclmch mce active delay (from clk) - 25 - 23 - 23 ns 1 (12) tsvlh ale active delay (from status) - 20 - 20 - 20 ns 1 (13) tsvmch mce active delay (from status) - 30 - 23 - 23 ns 1 (14) tchll ale inactive delay 4 18 4 18 4 18 ns 1 (15) tclml command active delay 5 35 5 35 5 35 ns 2 (16) tclmh command inactive delay 5 35 5 35 5 35 ns 2 (17) tchdtl direction control active delay - 50 - 50 - 50 ns 1 (18) tchdth direction control inactive delay - 30 - 30 - 30 ns 1 (19) taelch command enable time (note 1) - 40 - 40 - 40 ns 3 (20) taehcz command disable time (note 2) -40-40-40ns 4 (21) taelcv enable delay time 110 250 110 250 110 250 ns 2 (22) taevnv aen to den - 25 - 25 - 25 ns 1 (23) tcevnv cen to den, pden -25-25-25ns 1 (24) tcelrh cen to command - tclml +10 -tclml-tclmlns 2 (25) tlhll ale high time tclch - 10 - tclch - 10 - tclch - 10 nns 1 notes: 1. taelch measurement is between 1.5v and 2.5v. 2. taehcz measured at 0.5v change in vout. 1.5v 1.5v v il -0.4v input v ih +0.4v v ol output v oh table 2. test condition definition table test condition v1 r1 c1 12.13v220 ? 80pf 2 2.29v 91 ? 300pf 31.5v187 ? 300pf 41.5v187 ? 50pf test point v1 c1 (see note) r1 output from device under test note: includes stray and jig capacitance 82C88
339 timing waveforms (note 3) notes: 1. address/data bus is shown only for reference purposes. 2. leading edge of ale and mce is determined by the falling edge of clk or status going active. whichever occurs last. 3. all timing measurements are made at 1.5v unless otherwise specified. figure 1. state clk s2 , s1 , s0 address/data ale mrdc , iorc , inta , amwc , aiowc mwtc , iowc den (read) (inta) pden (read) (inta) den (write) pden (write) dt/r (read) (inta) mce t 4 t 1 t 2 t 3 t 4 tclcl (1) tclch (2) tchcl (3) tclsh (7) tshcl (6) tsvch (4) tchsv (5) tcllh (10) tsvlh (12) tchll (14) tclml (15) tclml (15) tclmh (16) tcvnx (9) tcvnv (8) tcvnv (8) tcvnx (9) tchdth (18) tchdtl (17) tchdth (18) tclmch (11) tsvmch (13) tcvnx (9) 2 2 1 write data valid address valid 82C88
340 figure 2. den, pden qualification timing figure 3. address enable (aen ) timing (three-state enable/disable) notes: 1. address/data bus is shown only for reference purposes. 2. leading edge of ale and mce is determined by the falling edge of clk or status going active. whichever occurs last. 3. all timing measurements are made at 1.5v unless otherwise specified. timing waveforms (note 3) (continued) taevnv (22) tcevnv (23) cen den aen pden cen taelcv (21) 1.5v taelch (19) voh tcelrh (24) tcelrh (24) taehcz (20) 1.5v 0.5v voh output command aen cen must be low or invalid prior to t2 to prevent the command from being generated. 82C88
341 burn-in circuits md82C88 cerdip mr82C88 clcc notes: 1. v cc = 5.5v 0.5v gnd = 0v 2. v ih = 4.5v 10% v il = -0.2v to +0.4v 3. component values: r1 = 47k ? , 1/4w, 5% r2 = 1.5k ? , 1/4w, 5% r3 = 10k ? , 1/4w, 5% r4 = 1.2k ? , 1/4w, 5% c1 = 0.01 f (min) f0 = 100khz 10% f1 = f0/2 f2 = f1/2 . . . f7 = f6/2 11 12 13 14 15 16 17 18 19 20 r1 r1 r2 r1 10 9 8 7 6 5 4 3 2 1 r2 r2 r1 r 3 r 3 v cc a c1 f5 f7 f0 f3 a a v cc a a a f2 v cc a a a a f4 f6 a a 4 5 6 7 8 9 10111213 3 2 1 20 19 15 14 18 17 16 r2 r4 r4 r1 r4 f2 v cc / 2 v cc / 2 f6 v cc / 2 r4 r4 r4 r4 v cc / 2 v cc / 2 r1 r4 r1 r4 v cc f0 f7 f3 f4 r4 r4 r1 r4 r4 v cc / 2 v cc / 2 v cc / 2 v cc / 2 f5 v cc c1 82C88
342 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 die characteristics die dimensions: 103.5 x 116.5 x 19 1mils metallization: type: si - al thickness: 11k ? 2k ? glassivation: type: nitrox thickness: 10k ? worst case current density: 1.9 x 10 5 a/cm 2 metallization mask layout 82C88 s1 clk iob v cc s0 s2 mce/ den cen inta iorc aiowc iowc gnd mwtc amwc mrdc aen ale dt/r pden 82C88
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